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[Crack Hack] rom_des

Description: DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm
Platform: | Size: 30720 | Author: | Hits:

[Embeded-SCM Develop] 148个verilog hdl小程序（有很多testbench）——

Description: 148个verilog hdl小程序（有很多testbench）——.-148 Verilog HDL small programs (many testbench) from Part
Platform: | Size: 55296 | Author: 地方 | Hits:

[VHDL-FPGA-Verilog] vhdl实现alu的源代码

Description: VHDL实现ALU的源代码，并且提供了一个详细的testbench！-ALU VHDL source code, and provide a detailed testbench!
Platform: | Size: 1024 | Author: 飞扬 | Hits:

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[Other] testbench

Description: 编写testbench的非常号的参考资料哦。-The preparation of the very issue of Testbench Reference Oh.
Platform: | Size: 244736 | Author: 文成 | Hits:

[Other] Testbench

Description: 单顶层结构化Testbench设计实例，适合硬件开发人员作为参考-Testbench structure of a single top-level design, suitable for hardware developers as a reference
Platform: | Size: 154624 | Author: xyq | Hits:

[Other] testbench

Description: 一片英语文章，详细描述了testbench的编写，尤其是assert和textio的用法，老外的文章就是不一样，看了之后让人茅塞顿开-An English article, a detailed description of the Testbench preparation, especially the use of assert and textio, a foreigner is not the same article, after seeing people茅塞顿开
Platform: | Size: 2094080 | Author: horse | Hits:

[VHDL-FPGA-Verilog] testbench

Description: 这是讲述如何编写testbench的，我认为很经典的。值得一看-This is how to prepare Testbench, I think is very classic. Worth a visit
Platform: | Size: 98304 | Author: 黄伟 | Hits:

[Software Engineering] testbench

Description: ritting testbench 入门级的还有XILINX的一篇文档how to write a testbench。你看看这个，看思想。-entry-level ritting testbench are XILINX a document how to write a testbench. You take a look at this, look at the ideological.
Platform: | Size: 2048 | Author: 老刘 | Hits:

[VHDL-FPGA-Verilog] testbench

Description: how to write testbench,use vhdl-how to write testbench, use vhdl
Platform: | Size: 90112 | Author: hxl | Hits:

[VHDL-FPGA-Verilog] vhdltestbench

Description: testbench,VHDL的，适合初学者使用-testbench
Platform: | Size: 321536 | Author: liushuai | Hits:

[Other] testbench

Description: 怎样编写仿真功能的测试文件（test bench）-Learning materials, how to prepare testbench
Platform: | Size: 2608128 | Author: sophie | Hits:

[VHDL-FPGA-Verilog] TestBench

Description: 怎样写testbench 本文的实际编程环境：ISE 6.2i.03 ModelSim 5.8 SE Synplify Pro 7.6 编程语言 VHDL 在ISE 中调用ModelSim 进行仿真-、assert (s_cyi((DWIDTH-1)/4) = 0 ) and (s_ovi = 0 ) and (s_qutnt = conv_std_logic_vector(v_quot,DWIDTH)) and (s_rmndr = conv_std_logic_vector(v_remd,DWIDTH)) report "ERROR in division!" severity failure
Platform: | Size: 90112 | Author: lei | Hits:

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[Crack Hack] rom_des

[Embeded-SCM Develop] 148个verilog hdl小程序（有很多testbench）——

[VHDL-FPGA-Verilog] vhdl实现alu的源代码

[VHDL-FPGA-Verilog] generic_fifo

[Other] testbench

[Other] Testbench

[Other] testbench

[VHDL-FPGA-Verilog] testbench

[Software Engineering] testbench

[VHDL-FPGA-Verilog] testbench

[VHDL-FPGA-Verilog] vhdltestbench

[Other] testbench

[VHDL-FPGA-Verilog] TestBench

[VHDL-FPGA-Verilog] uart-vhdl-testbench

[Windows Develop] testbench

[VHDL-FPGA-Verilog] testbench

[VHDL-FPGA-Verilog] testbench

[VHDL-FPGA-Verilog] testbench

[VHDL-FPGA-Verilog] testbench(vhdl)

[VHDL-FPGA-Verilog] VHDL--testbench

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